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1 /* me8100.h */ |
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2 /* Device driver for Meilhaus me1000 board. |
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3 * ======================================== |
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4 * |
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5 * Copyright (C) 2001 Meilhaus Electronic GmbH (support@meilhaus.de) |
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6 * |
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7 * This file is free software; you can redistribute it and/or modify |
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8 * it under the terms of the GNU General Public License as published by |
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9 * the Free Software Foundation; either version 2 of the License, or |
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10 * (at your option) any later version. |
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11 * |
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12 * This program is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 * GNU General Public License for more details. |
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16 * |
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17 * You should have received a copy of the GNU General Public License |
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18 * along with this program; if not, write to the Free Software |
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19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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20 */ |
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21 |
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22 |
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23 |
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24 /* |
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25 * Source File : me8100.h |
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26 * Destination : me8100.o |
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27 * Author : GG (Guenter Gebhardt) |
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28 * |
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29 * File History: Version Date Editor Action |
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30 *--------------------------------------------------------------------- |
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31 * 1.00.00 01.01.10 GG first release |
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32 * |
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33 * 1.00.01 01.02.14 GG Add new ioctls: |
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34 * get_board_info |
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35 * get_int count |
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36 * |
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37 * 1.01.00 01.10.08 GG Port to Kernel 2.4 |
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38 *--------------------------------------------------------------------- |
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39 * |
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40 * Description: |
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41 * |
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42 * Contains declarations and type definitions for the ME-8100 |
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43 * driver module. |
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44 * |
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45 */ |
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46 |
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47 |
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48 /* Please define this to enable debug mode */ |
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49 #undef ME8100_DEBUG |
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50 |
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51 #undef PDEBUG // only to be sure |
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52 |
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53 #ifdef ME8100_DEBUG |
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54 # define PDEBUG(fmt, args...) printk(KERN_DEBUG"ME8100:" fmt, ##args) |
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55 #else |
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56 # define PDEBUG(fmt, args...) // no debugging, do nothing |
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57 #endif |
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58 |
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59 |
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60 /* Meilhaus PCI vendor id */ |
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61 #define PCI_VENDOR_ID_MEILHAUS 0x1402 |
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62 |
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63 /* ME-8100 device IDs */ |
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64 #define PCI_DEVICE_ID_MEILHAUS_ME8100_A 0x0810A // Meilhaus ME8100 A |
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65 #define PCI_DEVICE_ID_MEILHAUS_ME8100_B 0x0810B // Meilhaus ME8100 B |
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66 |
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67 |
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68 /* Count of different ME-8100 sorts = 2 */ |
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69 #define SORT_COUNT 2 |
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70 |
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71 |
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72 /* Device name, for entries in /proc/.. */ |
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73 #define ME8100_NAME "me8100" |
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74 |
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75 |
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76 /* Maximum count of ME-8100 devices */ |
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77 #define ME8100_MAX_DEVICES 16 |
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78 |
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79 |
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80 /* Here you can enable the workaround for the plx bug */ |
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81 #define PLX_WORKAROUND_ENABLE 1 |
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82 |
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83 |
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84 /* Offset Interrupt Control Status Register of the PLX */ |
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85 #define PLX_ICSR 0x4C |
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86 |
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87 |
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88 /* Size of register bases */ |
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89 #define ME8100_BASE_SIZE 0xFF |
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90 #define PLX_BASE_SIZE 0x80 |
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91 |
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92 |
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93 /**************************************************/ |
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94 /* Bit definition for the ME8100_CTRL_REG_X */ |
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95 /* it differs from the ISA VERSION !!! */ |
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96 /* The other registers are similar to ISA VERSION */ |
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97 /**************************************************/ |
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98 // Bit 0-3 dont care |
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99 // Bit 4 SRC/SINK 1 = SRC 0 = SINK |
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100 // Bit 5 INTB 1 ISA has here INTB 0 |
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101 // Bit 6 INTB 0 ISA has here INTB 1 |
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102 // Bit 7 ENIO 1 = Enable 0 = high resistance |
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103 // Bit 8-15 dont care |
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104 /*********************************************************/ |
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105 /* The ME8100_ID_REG_X contains on PCI boards static 81h */ |
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106 /*********************************************************/ |
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107 |
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108 /* ME8100 Register Set A */ |
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109 #define ME8100_ID_REG_A 0x00 //(r, ) |
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110 #define ME8100_CTRL_REG_A 0x00 //( ,w) |
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111 #define ME8100_RES_INT_REG_A 0x02 //(r, ) |
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112 #define ME8100_DI_REG_A 0x04 //(r, ) |
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113 #define ME8100_DO_REG_A 0x06 //( ,w) |
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114 #define ME8100_PATTERN_REG_A 0x08 //( ,w) |
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115 #define ME8100_MASK_REG_A 0x0A //( ,w) |
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116 #define ME8100_INT_DI_REG_A 0x0A //(r, ) |
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117 |
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118 /* ME8100 Register Set B */ |
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119 #define ME8100_ID_REG_B 0x0C //(r, ) |
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120 #define ME8100_CTRL_REG_B 0x0C //( ,w) |
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121 #define ME8100_RES_INT_REG_B 0x0E //(r, ) |
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122 #define ME8100_DI_REG_B 0x10 //(r, ) |
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123 #define ME8100_DO_REG_B 0x12 //( ,w) |
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124 #define ME8100_PATTERN_REG_B 0x14 //( ,w) |
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125 #define ME8100_MASK_REG_B 0x16 //( ,w) |
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126 #define ME8100_INT_DI_REG_B 0x16 //(r, ) |
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127 |
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128 /* ME8100 82C54 Counter Registers */ |
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129 /* 82C54 registers are adressed as 8-bit registers, so the */ |
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130 /* offset is in bytes. */ |
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131 #define ME8100_COUNTER_REG_0 0x18 //(r,w) |
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132 #define ME8100_COUNTER_REG_1 0x1A //(r,w) |
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133 #define ME8100_COUNTER_REG_2 0x1C //(r,w) |
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134 #define ME8100_COUNTER_CTRL_REG 0x1E //(r,w) |
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135 |
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136 /* Bitmasks for the PLX_ICSR register */ |
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137 #define LOCAL_INT1_EN 0x01 // local interrupt 1 enabled (r,w) |
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138 #define LOCAL_INT1_POL 0x02 // local interrupt 1 polarity (r,w) |
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139 #define LOCAL_INT1_STATE 0x04 // local interrupt 1 state (r, ) |
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140 #define LOCAL_INT2_EN 0x08 // local interrupt 2 enabled (r,w) |
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141 #define LOCAL_INT2_POL 0x10 // local interrupt 2 polarity (r,w) |
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142 #define LOCAL_INT2_STATE 0x20 // local interrupt 2 state (r, ) |
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143 #define PCI_INT_EN 0x40 // PCI interrupt enable (r,w) |
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144 #define SOFT_INT 0x80 // Software interrupt (r,w) |
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145 |
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146 |
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147 typedef enum { |
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148 ME8100_A, |
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149 ME8100_B |
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150 } me8100_version_enum_type; |
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151 |
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152 |
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153 typedef struct{ |
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154 int int1; |
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155 int int2; |
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156 } me8100_int_occur_type; |
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157 |
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158 |
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159 typedef struct{ |
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160 int board_count; /* index of the board after detection */ |
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161 me8100_version_enum_type version; /* sort of board */ |
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162 unsigned int plx_regbase; /* PLX configuration space base address */ |
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163 unsigned int me8100_regbase; /* Base address of the ME8100/2000 */ |
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164 unsigned int plx_regbase_size; /* Size of PLX space */ |
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165 unsigned int me8100_regbase_size; /* Size of ME8100 base address */ |
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166 unsigned int serial_no; /* Serial number of the board */ |
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167 unsigned char hw_revision; /* Hardware revision of the board */ |
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168 unsigned short vendor_id; /* Meilhaus vendor id (0x1402) */ |
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169 unsigned short device_id; /* Device ID */ |
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170 int pci_bus_no; /* PCI bus number */ |
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171 int pci_dev_no; /* PCI device number */ |
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172 int pci_func_no; /* PCI function number */ |
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173 char int_line; /* IRQ assigned from the PCI BIOS */ |
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174 int int1; /* Marks witch interrupt occured */ |
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175 int int2; /* Marks witch interrupt occured */ |
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176 int int_count_1; /* Count of interrupt 1 */ |
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177 int int_count_2; /* Count of interrupt 2 */ |
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178 int board_in_use; /* Indicates if board is already in use */ |
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179 spinlock_t use_lock; /* Guards board in use */ |
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180 struct file *file_ptr; /* Pointer to file structure of path */ |
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181 } me8100_info_type; |
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182 |
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183 |
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184 /* ME8100 IOCTL's */ |
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185 #define ME8100_IOCTL_MAXNR 29 |
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186 #define ME8100_MAGIC 'o' |
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187 #define ME8100_READ_ID_A _IOR(ME8100_MAGIC, 0, unsigned short) |
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188 #define ME8100_WRITE_CTRL_A _IOW(ME8100_MAGIC, 1, unsigned short) |
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189 #define ME8100_RES_INT_A _IOR(ME8100_MAGIC, 2, unsigned short) |
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190 #define ME8100_READ_DI_A _IOR(ME8100_MAGIC, 3, unsigned short) |
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191 #define ME8100_WRITE_DO_A _IOW(ME8100_MAGIC, 4, unsigned short) |
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192 #define ME8100_WRITE_PATTERN_A _IOW(ME8100_MAGIC, 5, unsigned short) |
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193 #define ME8100_WRITE_MASK_A _IOW(ME8100_MAGIC, 6, unsigned short) |
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194 #define ME8100_READ_INT_DI_A _IOR(ME8100_MAGIC, 7, unsigned short) |
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195 |
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196 #define ME8100_READ_ID_B _IOR(ME8100_MAGIC, 8, unsigned short) |
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197 #define ME8100_WRITE_CTRL_B _IOW(ME8100_MAGIC, 9, unsigned short) |
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198 #define ME8100_RES_INT_B _IOR(ME8100_MAGIC, 10, unsigned short) |
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199 #define ME8100_READ_DI_B _IOR(ME8100_MAGIC, 11, unsigned short) |
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200 #define ME8100_WRITE_DO_B _IOW(ME8100_MAGIC, 12, unsigned short) |
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201 #define ME8100_WRITE_PATTERN_B _IOW(ME8100_MAGIC, 13, unsigned short) |
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202 #define ME8100_WRITE_MASK_B _IOW(ME8100_MAGIC, 14, unsigned short) |
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203 #define ME8100_READ_INT_DI_B _IOR(ME8100_MAGIC, 15, unsigned short) |
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204 |
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205 #define ME8100_WRITE_COUNTER_0 _IOW(ME8100_MAGIC, 16, unsigned char) |
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206 #define ME8100_WRITE_COUNTER_1 _IOW(ME8100_MAGIC, 17, unsigned char) |
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207 #define ME8100_WRITE_COUNTER_2 _IOW(ME8100_MAGIC, 18, unsigned char) |
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208 #define ME8100_READ_COUNTER_0 _IOR(ME8100_MAGIC, 19, unsigned char) |
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209 #define ME8100_READ_COUNTER_1 _IOR(ME8100_MAGIC, 20, unsigned char) |
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210 #define ME8100_READ_COUNTER_2 _IOR(ME8100_MAGIC, 21, unsigned char) |
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211 #define ME8100_SETUP_COUNTER _IOW(ME8100_MAGIC, 22, unsigned char) |
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212 |
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213 #define ME8100_GET_SERIAL _IOR(ME8100_MAGIC, 23, unsigned int) |
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214 #define ME8100_GET_NAME _IOR(ME8100_MAGIC, 24,me8100_version_enum_type) |
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215 #define ME8100_INT_OCCUR _IOR(ME8100_MAGIC, 25, me8100_int_occur_type) |
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216 #define ME8100_SETUP_ICSR _IOW(ME8100_MAGIC, 26, unsigned char) |
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217 #define ME8100_READ_ICSR _IOR(ME8100_MAGIC, 27, unsigned char) |
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218 #define ME8100_GET_BOARD_INFO _IOR(ME8100_MAGIC, 28, me8100_info_type) |
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219 #define ME8100_GET_INT_COUNT _IOR(ME8100_MAGIC, 29, me8100_int_occur_type) |