45  */

    45  */

    46 

    46 

    47 

    47 

    48 /* Please define this to enable debug mode */

    48 /* Please define this to enable debug mode */

    49 #undef ME8100_DEBUG

    49 #undef ME8100_DEBUG

    50 

    51 

    51 #undef PDEBUG // only to be sure

    52 #undef PDEBUG // only to be sure

    52 

    53 

    53 #ifdef ME8100_DEBUG

    54 #ifdef ME8100_DEBUG

    55 #else 

    56 #else 

    56 # define PDEBUG(fmt, args...) // no debugging, do nothing

    57 # define PDEBUG(fmt, args...) // no debugging, do nothing

    57 #endif

    58 #endif

    58 

    59 

    59 

    60 

    99 // Bit 4   SRC/SINK    1 = SRC  0 = SINK

   100 // Bit 4   SRC/SINK    1 = SRC  0 = SINK

   100 // Bit 5   INTB 1      ISA has here INTB 0

   101 // Bit 5   INTB 1      ISA has here INTB 0

   101 // Bit 6   INTB 0      ISA has here INTB 1

   102 // Bit 6   INTB 0      ISA has here INTB 1

   102 // Bit 7   ENIO        1 = Enable  0 = high resistance

   103 // Bit 7   ENIO        1 = Enable  0 = high resistance

   103 // Bit 8-15 dont care

   104 // Bit 8-15 dont care

   104 /*********************************************************/

   125 /*********************************************************/

   105 /* The ME8100_ID_REG_X contains on PCI boards static 81h */

   126 /* The ME8100_ID_REG_X contains on PCI boards static 81h */

   106 /*********************************************************/

   127 /*********************************************************/

   107 

   136 

   108 /* ME8100 Register Set A */

   137 /* ME8100 Register Set A */

   109 #define ME8100_ID_REG_A			0x00      //(r, )

   138 #define ME8100_ID_REG_A			0x00      //(r, )

   110 #define ME8100_CTRL_REG_A		0x00      //( ,w)

   139 #define ME8100_CTRL_REG_A		0x00      //( ,w)

   111 #define ME8100_RES_INT_REG_A		0x02      //(r, )

   140 #define ME8100_RES_INT_REG_A		0x02      //(r, )

   112 #define ME8100_DI_REG_A			0x04      //(r, )

   141 #define ME8100_DI_REG_A			0x04      //(r, )

   113 #define ME8100_DO_REG_A                 0x06      //( ,w)

   142 #define ME8100_DO_REG_A                 0x06      //( ,w)

   114 #define ME8100_PATTERN_REG_A		0x08      //( ,w)

   143 #define ME8100_PATTERN_REG_A		0x08      //( ,w)

   115 #define ME8100_MASK_REG_A		0x0A      //( ,w)

   144 #define ME8100_MASK_REG_A		0x0A      //( ,w)

   116 #define ME8100_INT_DI_REG_A		0x0A      //(r, )

   145 #define ME8100_INT_DI_REG_A		0x0A      //(r, )

   117 									

   147 									

   118 /* ME8100 Register Set B */		

   148 /* ME8100 Register Set B */		

   119 #define ME8100_ID_REG_B			0x0C      //(r, )

   149 #define ME8100_ID_REG_B			0x0C      //(r, )

   120 #define ME8100_CTRL_REG_B		0x0C      //( ,w)

   150 #define ME8100_CTRL_REG_B		0x0C      //( ,w)

   121 #define ME8100_RES_INT_REG_B		0x0E      //(r, )

   151 #define ME8100_RES_INT_REG_B		0x0E      //(r, )

   153 typedef struct{

   183 typedef struct{

   154   int int1;

   184   int int1;

   155   int int2;

   185   int int2;

   156 } me8100_int_occur_type;

   186 } me8100_int_occur_type;

   157 

   187 

   158 

   189 

   159 typedef struct{

   190 typedef struct{

   160   int board_count;                  /* index of the board after detection    */

   191   int board_count;                  /* index of the board after detection    */

   161   me8100_version_enum_type version; /* sort of board                         */

   192   me8100_version_enum_type version; /* sort of board                         */

   162   unsigned int plx_regbase;         /* PLX configuration space base address  */

   193   unsigned int plx_regbase;         /* PLX configuration space base address  */

   176   int int_count_1;                  /* Count of interrupt 1                  */

   207   int int_count_1;                  /* Count of interrupt 1                  */

   177   int int_count_2;                  /* Count of interrupt 2                  */

   208   int int_count_2;                  /* Count of interrupt 2                  */

   178   int board_in_use;                 /* Indicates if board is already in use  */

   209   int board_in_use;                 /* Indicates if board is already in use  */

   179   spinlock_t use_lock;              /* Guards board in use                   */

   210   spinlock_t use_lock;              /* Guards board in use                   */

   180   struct file *file_ptr;            /* Pointer to file structure of path     */

   211   struct file *file_ptr;            /* Pointer to file structure of path     */

   181 } me8100_info_type;

   213 } me8100_info_type;

   182 

   214 

   183 

   216 

   184 /* ME8100 IOCTL's */

   217 /* ME8100 IOCTL's */

   185 #define ME8100_IOCTL_MAXNR 29

   218 #define ME8100_IOCTL_MAXNR 29

   186 #define ME8100_MAGIC 'o'

   219 #define ME8100_MAGIC 'o'

   187 #define ME8100_READ_ID_A        _IOR(ME8100_MAGIC, 0,  unsigned short)

   220 #define ME8100_READ_ID_A        _IOR(ME8100_MAGIC, 0,  unsigned short)

   215 #define ME8100_INT_OCCUR        _IOR(ME8100_MAGIC, 25, me8100_int_occur_type)

   248 #define ME8100_INT_OCCUR        _IOR(ME8100_MAGIC, 25, me8100_int_occur_type)

   216 #define ME8100_SETUP_ICSR       _IOW(ME8100_MAGIC, 26, unsigned char)

   249 #define ME8100_SETUP_ICSR       _IOW(ME8100_MAGIC, 26, unsigned char)

   217 #define ME8100_READ_ICSR        _IOR(ME8100_MAGIC, 27, unsigned char)

   250 #define ME8100_READ_ICSR        _IOR(ME8100_MAGIC, 27, unsigned char)

   218 #define ME8100_GET_BOARD_INFO   _IOR(ME8100_MAGIC, 28, me8100_info_type)

   251 #define ME8100_GET_BOARD_INFO   _IOR(ME8100_MAGIC, 28, me8100_info_type)

   219 #define ME8100_GET_INT_COUNT    _IOR(ME8100_MAGIC, 29, me8100_int_occur_type)

   252 #define ME8100_GET_INT_COUNT    _IOR(ME8100_MAGIC, 29, me8100_int_occur_type)