71 oflags = fcntl(file_handle, F_GETFL); |
66 oflags = fcntl(file_handle, F_GETFL); |
72 |
67 |
73 /* Inform the driver to put the current process on the fasync queue */ |
68 /* Inform the driver to put the current process on the fasync queue */ |
74 fcntl(file_handle, F_SETFL, oflags | FASYNC); |
69 fcntl(file_handle, F_SETFL, oflags | FASYNC); |
75 |
70 |
76 /* enable both interrupts on the plx, set interrupts to high active */ |
71 printf("Waiting for Interrupts\n\n"); |
77 icsr = |
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78 LOCAL_INT1_EN | |
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79 LOCAL_INT1_POL | |
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80 PCI_INT_EN; |
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81 |
72 |
82 err = ioctl(file_handle, ME8100_SETUP_ICSR, &icsr); |
73 for(;;) { |
83 if(err){ |
74 sleep(10); |
84 printf("Cannot setup PLX\n"); |
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85 return 1; |
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86 } |
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87 |
|
88 /*-------------------- Interrupt caused by bit mask -----------------*/ |
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89 |
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90 /* Set the proper bit mask for port a */ |
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91 mask_a = 0xffff; |
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92 err = ioctl(file_handle, ME8100_WRITE_MASK_A, &mask_a); |
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93 if(err){ |
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94 printf("Cannot write mask a\n"); |
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95 return 1; |
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96 } |
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97 |
|
98 /* Enable interrupt signalling by bit mask for port a */ |
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99 ctrl_a = ME8100_CTRL_ENIO | ME8100_CTRL_SOURCE | ME8100_CTRL_IRQ_MASK; |
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100 err = ioctl(file_handle, ME8100_WRITE_CTRL_A, &ctrl_a); |
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101 if(err){ |
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102 printf("Cannot write ctrl a\n"); |
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103 return 1; |
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104 } |
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105 |
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106 printf("<<<--- WAITING FOR INTERRUPTS BY BIT MASK --->>>\n\n"); |
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107 |
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108 i = 0; |
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109 while(i < 1000) { |
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110 select(0, NULL, NULL, NULL, NULL); |
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111 } |
75 } |
112 |
76 |
113 printf("Close path to me8100_0\n"); |
77 printf("Close path to me8100_0\n"); |
114 err = close(file_handle); |
78 err = close(file_handle); |
115 if(err){ |
79 if(err){ |