diff -r c3f6d5e9713a -r b9baa645576a me8100_test_int/test.c
--- a/me8100_test_int/test.c	Mon Jan 21 21:52:00 2002 +0100
+++ b/me8100_test_int/test.c	Tue Jan 22 20:30:44 2002 +0100
@@ -45,11 +45,6 @@
   int err = 0;
   int oflags = 0;
 
-  unsigned short mask_a;
-  unsigned short ctrl_a;
-
-  unsigned char icsr;
-
   printf("IRQ Test %d\n", getpid());
 
   file_handle = open("/dev/me8100_0a", O_RDONLY, 0);
@@ -73,41 +68,10 @@
   /* Inform the driver to put the current process on the fasync queue */
   fcntl(file_handle, F_SETFL, oflags | FASYNC); 
 
-  /* enable both interrupts on the plx, set interrupts to high active */
-  icsr =
-    LOCAL_INT1_EN |
-    LOCAL_INT1_POL |
-    PCI_INT_EN;
-
-  err = ioctl(file_handle, ME8100_SETUP_ICSR, &icsr);
-  if(err){
-    printf("Cannot setup PLX\n");
-    return 1;
-  }
-
-  /*-------------------- Interrupt caused by bit mask -----------------*/
+  printf("Waiting for Interrupts\n\n");
 
-  /* Set the proper bit mask for port a */
-  mask_a = 0xffff;
-  err = ioctl(file_handle, ME8100_WRITE_MASK_A, &mask_a);
-  if(err){
-    printf("Cannot write mask a\n");
-    return 1;
-  }
-
-  /* Enable interrupt signalling by bit mask for port a */
-  ctrl_a = ME8100_CTRL_ENIO | ME8100_CTRL_SOURCE | ME8100_CTRL_IRQ_MASK;
-  err = ioctl(file_handle, ME8100_WRITE_CTRL_A, &ctrl_a);
-  if(err){
-    printf("Cannot write ctrl a\n");
-    return 1;
-  }
-
-  printf("<<<--- WAITING FOR INTERRUPTS BY BIT MASK --->>>\n\n");
-
-  i = 0;
-  while(i < 1000) {
-    select(0, NULL, NULL, NULL, NULL);
+  for(;;) {
+    sleep(10);
   }
 
   printf("Close path to me8100_0\n");