604 |
604 |
605 PDEBUG("*** open for writing\n"); |
605 PDEBUG("*** open for writing\n"); |
606 |
606 |
607 if (0 == subinfo->num_writer++) { |
607 if (0 == subinfo->num_writer++) { |
608 subinfo->ctrl_reg |= ME8100_CTRL_ENIO | ME8100_CTRL_SOURCE; |
608 subinfo->ctrl_reg |= ME8100_CTRL_ENIO | ME8100_CTRL_SOURCE; |
609 PDEBUG("*** adding ENIO+SOURCE mode: ctrl: 0x%x\n", subinfo->ctrl_reg); |
609 PDEBUG("*** adding %0x to ctrl: 0x%04x\n", |
|
610 ME8100_CTRL_ENIO | ME8100_CTRL_SOURCE, subinfo->ctrl_reg); |
610 outw(subinfo->ctrl_reg, subinfo->regbase + ME8100_CTRL_REG); |
611 outw(subinfo->ctrl_reg, subinfo->regbase + ME8100_CTRL_REG); |
611 } |
612 } |
612 } |
613 } |
613 |
614 |
614 |
615 |
620 |
621 |
621 struct me8100_private_data *priv; |
622 struct me8100_private_data *priv; |
622 |
623 |
623 PDEBUG("*** open for reading\n"); |
624 PDEBUG("*** open for reading\n"); |
624 |
625 |
625 if (!(priv = kmalloc(sizeof(*priv), GFP_KERNEL))) { |
626 if (0 == subinfo->num_reader++) { |
626 printk(KERN_ERR"ME8100:me8100_open: kmalloc() failed.\n"); |
627 |
627 me8100_release(inode_ptr, file_ptr); |
628 PDEBUG("*** first reader...\n"); |
628 return -EIO; |
629 |
629 } |
630 if (!(priv = kmalloc(sizeof(*priv), GFP_KERNEL))) { |
630 |
631 printk(KERN_ERR"ME8100:me8100_open: kmalloc() failed.\n"); |
631 priv->last_read = 0; |
632 me8100_release(inode_ptr, file_ptr); |
632 file_ptr->private_data = priv; |
633 return -EIO; |
633 |
634 } |
634 /* Now we've to setup the IRQ line. We suppose that it should be done |
635 |
635 * in "mask" manner. If somebody wishes to do it the otherway or if somebody |
636 priv->last_read = 0; |
636 * wants to change the mask, ioctl() should be used. */ |
637 file_ptr->private_data = priv; |
637 { |
638 |
638 int mask = 0xffff; |
639 /* Now we've to setup the IRQ line. We suppose that it should be done |
639 unsigned short icsr = PCI_INT_EN | ((LOCAL_INT_EN | LOCAL_INT_POL) << (3 * subdevice)); |
640 * in "mask" manner. If somebody wishes to do it the otherway or if somebody |
640 |
641 * wants to change the mask, ioctl() should be used. */ |
641 |
642 { |
642 /* 1) setup the PLX register */ |
643 int mask = 0xffff; |
643 PDEBUG("*** plx = 0x%0x\n", icsr); |
644 unsigned short icsr = PCI_INT_EN | ((LOCAL_INT_EN | LOCAL_INT_POL) << (3 * subdevice)); |
644 outb(icsr, info->plx_regbase + PLX_ICSR); |
645 |
645 |
646 |
646 /* 2) setup the irq flags in regbase */ |
647 /* 1) setup the PLX register */ |
647 subinfo->ctrl_reg |= ME8100_CTRL_IRQ_MASK; |
648 PDEBUG("*** plx = 0x%0x\n", icsr); |
648 PDEBUG("*** ctrl = 0x%04x\n", subinfo->ctrl_reg); |
649 outb(icsr, info->plx_regbase + PLX_ICSR); |
649 outw(subinfo->ctrl_reg, subinfo->regbase + ME8100_CTRL_REG); |
650 |
650 |
651 /* 2) setup the irq flags in regbase */ |
651 /* 3) setup the interrupt mask */ |
652 subinfo->ctrl_reg |= ME8100_CTRL_IRQ_MASK; |
652 PDEBUG("*** irqmask = 0x%04x\n", mask); |
653 PDEBUG("*** adding %0x to ctrl: 0x%04x\n", ME8100_CTRL_IRQ_MASK, |
653 outw(mask, subinfo->regbase + ME8100_MASK_REG); |
654 subinfo->ctrl_reg); |
654 |
655 outw(subinfo->ctrl_reg, subinfo->regbase + ME8100_CTRL_REG); |
655 } |
656 |
656 } |
657 /* 3) setup the interrupt mask */ |
|
658 PDEBUG("*** irqmask = 0x%04x\n", mask); |
|
659 outw(mask, subinfo->regbase + ME8100_MASK_REG); |
|
660 |
|
661 } |
|
662 } /* first reader */ |
|
663 } /* reader */ |
657 |
664 |
658 |
665 |
659 return 0; |
666 return 0; |
660 } |
667 } |
661 |
668 |
703 /* Resetting write mode if last writer is gone */ |
710 /* Resetting write mode if last writer is gone */ |
704 if (file_ptr->f_mode & FMODE_WRITE) { |
711 if (file_ptr->f_mode & FMODE_WRITE) { |
705 PDEBUG("*** writer closes\n"); |
712 PDEBUG("*** writer closes\n"); |
706 if (0 == --subinfo->num_writer) { |
713 if (0 == --subinfo->num_writer) { |
707 subinfo->ctrl_reg &= !ME8100_CTRL_ENIO; |
714 subinfo->ctrl_reg &= !ME8100_CTRL_ENIO; |
708 // PDEBUG("*** resetting ENIO mode ctrl: 0x%x\n", subinfo->ctrl_reg); |
715 PDEBUG("*** resetting ENIO mode ctrl: 0x%x\n", subinfo->ctrl_reg); |
709 // outw(subinfo->ctrl_reg, subinfo->regbase + ME8100_CTRL_REG); |
716 outw(subinfo->ctrl_reg, subinfo->regbase + ME8100_CTRL_REG); |
710 } |
717 } |
711 } |
718 } |
|
719 |
|
720 if (file_ptr->f_mode & FMODE_READ) { |
|
721 PDEBUG("*** reader close\n"); |
|
722 if (0 == --subinfo->num_reader) { |
|
723 PDEBUG("*** last reader...\n"); |
|
724 subinfo->ctrl_reg &= !ME8100_CTRL_IRQ_MASK; /* 11 */ |
|
725 PDEBUG("*** resetting IRQ mode ctrl: 0x%x\n", subinfo->ctrl_reg); |
|
726 outw(subinfo->ctrl_reg, subinfo->regbase + ME8100_CTRL_REG); |
|
727 } |
|
728 } |
|
729 |
712 |
730 |
713 /* resetting the board on last close */ |
731 /* resetting the board on last close */ |
714 |
732 |
715 if (--info->board_in_use == 0) { |
733 if (--info->board_in_use == 0) { |
716 err = me8100_reset_board(info); |
734 err = me8100_reset_board(info); |